Area-efficient FPGA post-quantum cryptography module
* Developed an architecture including the following innovations: - Optimized the NTT algorithm with GS butterfly. The GS butterfly is used both in forward and inverse NTT to utilize the internal DSP adders. The optimization reduces about 30% clock cycles compared with the textbook implementations. - Developed a dual-column sequential storage scheme that keeps the pipelined datapath free of bubbles. - Integrating NTT, multiply-accumulate (MACC) and multiply-add (MADD) operations using only 442 LUTs and 237 FFs. The module achieves at least 3x more efficient than the state of work.